Part A (10X2=20 Marks)
1.
Convert
(125.62)8 to binary equivalent.
2. What is combinational circuit? Give examples.
3.
What
are the advantages and disadvantages of CMOS family?
4.
Define
noise margin.
5.
What
are the major difference between ECL and TTL?
6.
Simplify
the following logical expression using karnaugh map Y=A’B’C’+A’BC’+AB’C’+A’B’C+ABC’.
7.
Simplify
the following function f(A,B,C,D)= Σm(0,1,2,3,11,12,14,15).
8.
Draw
the logic diagram of Ex-OR gate and its truth table.
9.
Define
min term and max term.
10. Convert the given expression in
standard POS from f(A,B,C)=(A+B).(A+C)
PART
B (13X5=65 Marks)
11. Explain the characteristics of
Digital logic families.(13)
12. Explain and detail about TTL.(13)
13. Explain the operation of a half
subtractor and full subtractor with the help of logic diagram, truth table and
k-map.(13)
14. a) Convert the given expression
in standard POS form y=A.(A+B+C)(6)
b) Reduce the following function
using k –map technique f(w,x,y,z)=Σm(0,7,8,9,10,12)+Σd(2,5,13) (7)
15. a)Simplify
using k-map to obtain a minimum POS expression(A’+B’+C+D) (A+B’+C+D) (A+B+C+D’)
(A+B+C’+D’) (A’+B+C+D’) (A+B+C’+D) (6)
b) Simplify the following function using K – map,
f=ABCD+AB'C’D’+AB’C+AB &
realize the SOP using only NAND gates (7)
realize the SOP using only NAND gates (7)
PART
C (15X1=15 Marks)
16.
Design & implement the conversion
circuits for
4- bit binary to BCD Converter.
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